library ieee;
use ieee.std_logic_1164.all;

package processor_types is
    
    subtype bit64 is std_logic_vector(63 downto 0);
    subtype bit33 is std_logic_vector(32 downto 0);
	subtype bit32 is std_logic_vector(31 downto 0);
    subtype bit26 is std_logic_vector(25 downto 0);
    subtype bit16 is std_logic_vector(15 downto 0);
    subtype bit6 is std_logic_vector(5 downto 0);
    subtype bit5 is std_logic_vector(4 downto 0);
    subtype bit2 is std_logic_vector(1 downto 0);
    subtype bit3 is std_logic_vector(2 downto 0);
    
    type registers32 is array (natural range 0 to 31) of bit32;
    
    constant dontcare : bit32 := (others => '-');
    
    -- opcodes
    constant rtype  : bit6 := "000000";
    constant blez   : bit6 := "000110";
    constant j      : bit6 := "000010";
    constant lw     : bit6 := "100011";
    constant sw     : bit6 := "101011";
    
    -- function codes for r-type
    --constant add    : bit6 := "100000";
    constant add    : bit6 := "100001"; -- this is actually the addu function
    constant mfhi   : bit6 := "010000";
    constant mflo   : bit6 := "010010";
    constant mult   : bit6 := "011000";
    constant f_sll  : bit6 := "000000";
    constant sltu   : bit6 := "101011";
    constant f_nor  : bit6 := "100111";
    
    type alu_signals is
        (addition, subtract, not_or, setltu, shiftleft, gethigh, getlow, init_mult, shiftright);

	type alu_input_select is
        (rs_rt, pc_imm, pc_address, rt_rh, rs_imm, res_rt, res_null);
		
    type alu_bus is array (alu_signals) of std_ulogic;

end processor_types;